By John M. Levesque
Contents: advent; Supercomputer structure; Fortran; Vectorization of Fortran courses. Index. This e-book explains intimately either the underlying structure of brand new supercomputers and the way in which a compiler maps Fortran code onto that structure. most crucial, the constructs combating complete optimizations are defined, and particular options for restructuring a application are supplied
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Extra resources for A Guidebook to Fortran on Supercomputers
A loop in which almost every arithmetic operation is matched with a memory fetch or store of a vector). The Cray-1, Cray-IS, and Cray-2 each have one path into main memory, and it provides both fetching and storing of data but not both at the same time. The Cray X-MP has two fetch paths and one store path, all of which can operate concurrently. 2 THE VECTOR PROCESSOR 39 The Cray X-MP, with its extra memory paths: • Fetches the vector B(l:64) to a vector register, while simultaneously fetching C(l:64), and, as soon as B(l) and C(l) have arrived, begins adding the vectors together, placing the results in a third vector register while simultaneously storing the results into A(l:64).
Problems 1. Consider a memory-bank structure that has 256 banks, and the bank cycle time is 64 clock cycles. If the memory functional-unit time is 25 + N, how long would it take, in clock cycles, to fetch 64 words from memory with strides of 1, 2, 4, 8, 16, 32, 64, 128, and 256? 2. The major bottleneck on a SISD machine is that only a single instruction can be issued each clock cycle. Explain how the following machines overcome this bottleneck and what category (SIMD or MIMD) each are: a. Uniprocessor of a Cray X-MP in vector mode.
3, calculate the time needed for each method as a function of S. If S = 1, method 2 is faster; if S = 500, method 1 is faster. For what stride (S) does method 1 first become faster than method 2 for a 4-pipe CYBER 205 in 32-bit mode? For a 2-pipe CYBER 205 in 64-bit mode? 4. Vectorization of IF constructs on the CYBER 205 can be performed using bit vectors to control storage into the arrays. EPSLON, how often must the condition be true before the "controlled-store" approach runs faster than the compress/ expand approach?